Recently, demand for nonvolatile semiconductor memory devices which are compact and have large capacity have been increasing rapidly. Among these, a NAND type flash memory, in which higher integration and larger capacity are expected as compared with a conventional NOR type flash memory, has attracted attention.
In the program operation of a conventional NAND type flash memory, Self Boost Method (SB) is used, wherein NAND cell units including memory cells which are not to be programmed are separated from bit lines and the potential of the channels of the memory cells which are not to be programmed are raised up to a predetermined program inhibition potential by capacitive coupling with the word lines, so that inhibits to program into memory cells which are not to be programmed (which are not to be injected with electrons) sharing word lines (Selected word lines) with selected memory cells which are to be programmed. Data programming operation of conventional NAND type flash memories using the SB methods is as follows.
In FIG. 13, changes of set potential waveform of word lines WL0 to WL7 of a NAND cell unit in the data programming operation are shown. The data programming operation of the NAND type flash memory has been performed, usually, sequentially from memory cells at the remotest position from the bit lines.
First, when a data programming operation is initiated, in response to program data, Vss (ground potential, e.g., 0V) are applied when “0” data programming, and Vcc (power supply voltage, e.g., 3V) are applied when “1” data programming, on bit lines of selected NAND cell unit; and Vcc is applied to a selected bit line side selection gate line. In this case, when the bit line is Vss (“0” data programming), in the selected NAND cell unit, channels inside of the NAND cell are fixed to Vss via the selection gate transistor in the selected NAND cell unit connected to the bit line. When the bit line is Vcc (“1” data programming), channels inside of the NAND cell in the connected selected NAND cell unit are charged to [Vcc-Vtsg] (note that Vtsg is the threshold voltage of the selection gate transistor, e.g., about 1.5 V) via the selection gate transistor, and then achieves a “floating state.”
Subsequently, at the timing t1, unselected word lines in the selected NAND cell unit are raised from Vss to Vpass (pass potential, e.g., 10V), then at the timing t2 the word lines in the selected NAND cell units are raised from Vss to Vpgm (high voltage for programming, e.g., 20 V). FIG. 13 shows an example of a memory cell connected to word line WL2 is a selected memory cell, and the memory cells connected to the other word lines WL0, WL1 and WL3 to WL7 are unselected memory cells.
Here, when the bit line is Vss (“0” data programming), in the selected NAND cell unit connected to the bit line, a large potential difference (about 20V) occurs between the gate (Vpgm potential) and the channel (Vss potential) of the selected memory cell inside of the selected NAND cell unit because the channel in the NAND cell is fixed to Vss, which in turn causes injections of electrons from the channel into the floating gate of the selected memory cell. Hereby, the threshold of the selected memory cell shifts to a positive direction. The state where the electrons are sufficiently injected in the floating gate is “0.”
On the other hand, when the bit line is at Vcc (“1” data programming), the channel in the NAND memory cell is in a floating state in the selected NAND cell unit connected to the bit line. Therefore, by influence of capacitive coupling between word lines and the channel, potential of the channel is raised from [Vcc-Vtsg] potential to Vmch potential (program inhibition potential: about 8V), being kept at floating state, accompanied by a rise in the voltage of the word lines (Vss to Vpgm or Vpass). At this time, electron injection does not occur because the potential difference between the gate (Vpgm potential) and the channel (Vmch potential) of the selected memory cell in the selected NAND cell unit is relatively small (about 12 V). Therefore, the threshold of the memory cell is not changed and is kept in a minus state. This state is a data “1.” See Japanese Patent Application Laid-open Disclosure No. 2000-228,097 and June Lee, et al., “A 1.8V 2 GB NAND Flash Memory for Mass Storage Applications”, 2003 IEEE International Solid-State Circuits Conference, Session 16, pp 236-pp 237.
In the programming operation of the conventional NAND type flash memory described above, at “1” data programming, the channel of the selected memory cell is in a floating state. Therefore, by influence of the capacitive coupling between the word line and the channel, the potential of the channel is raised from [Vcc-Vtsg] potential to Vmch potential, and is kept in a floating state, accompanied by a rise in the voltage of the word lines (Vss to Vpgm or Vpass). However, the potential of the channel could be overly raised from the floating state. Therefore, a surface stress is given in the memory cell having a low control gate potential (Vpass potential: 10 V) adjacent to the memory cell in which data will be programmed. Then electric charges are leaked from the floating channel, i.e., GIDL (Gate Induced Drain Leakage) may occur. By the GIDL, electric charges are easily injected into the floating gate of unselected memory cell adjacent to the selected memory cell. As a result, program errors can easily occur.
Also, FIG. 14 shows a method for supplying a pass potential Vpass first, and then supplying a high potential to programming Vpgm, in the control gate of the selected memory cell, which is described in Japanese Patent Application Laid-open Disclosure No. 2000-228,097 and “A 1.8V 2 GB NAND Flash Memory for Mass Storage Applications”, (June Lee, et al., 2003 IEEE International Solid-State Circuits Conference, Session 16, p 236 to p 237).
In the conventional method, however, GIDL may not be thoroughly prevented; especially when “1” data programming, leading to program errors and a deterioration in the reliability of the NAND type flash memory.
In a so-called “single level” program whose program data are either “0” or “1,” SB method is used. On the other hand, a so-called “multi level” program data, a threshold (Vth) distribution of the memory cells will be wider than the case of two level programming, allowing for plenty of memory cells with a high threshold (Vth). Therefore, a method is used in which the SB method is performed by dividing channels of memory cells closer to the bit line than a memory cell in which programming is performed; and channels of memory cells at the source side. Such a method is called EASB (Erase Area Self Boost) method.
As shown in FIG. 15 (a), the EASB method is a method wherein: a program voltage Vpgm is supplied to a selected word line in which programming is performed; a ground voltage Vss is supplied to a word line adjacent toward the source line side of the selected word line; and an intermediate voltage Vpass is supplied to the other word lines. The advantage of the EASB method is a higher boost efficiency because memory cells closer to the bit line than the memory cell to be programmed are thoroughly at the erased state when programming is performed sequentially from the memory cells in the source side; and thus channel potential of the memory cells can be boosted higher for “1” programming. On the other hand, the disadvantage of the EASB method is that a coupling ratio of the floating gate of the programming memory cells becomes lower when “0” programming is performed, because a potential of the word lines adjacent to the source line side from the selected word line is Vss.
Now, in order to deal with the above disadvantage of the EASB method, a program method, in which the bias method of the EASB method is changed, is used. This method is called an EASB-2 method.
As shown in FIG. 15 (b), the EASB-2 method is a method, wherein: a program voltage Vpgm is supplied to a selected word line in which programming is performed; a ground voltage Vss is supplied to a word line which is the second adjacent word line toward the source line end from the selected word line; and an intermediate voltage Vpass is supplied to the other word lines. The advantage of the EASB-2 method is, compared with those of the EASB method, a coupling ratio of the floating gate of the program cell is raised when “0” programming, so the program voltage Vpgm can be lowered; further there is an advantage that, at “1” programming the memory cells of the bit line side are one more than the program memory cells, and therefore a capacitance of the memory cell channel is larger, so that program errors caused by the leakage current at the channel boost period tend not to occur. However, there is a disadvantage in both the EASB method and EASB-2 method, that the closer the selected word lines to the bit line, the higher the boost effect becomes in the memory cells on the bit line side, than in the program memory cells, and thus the potential of the memory cell channels become too high. In the following, a problem in the case that the potential of the memory cell channels become too high by the EASB-2 method will be discussed in detail referring to FIG. 16.
In the EASB-2 method, at “1” programming, CG (n−1) is set at 0 V and CG (n) is boosted at Vpass (FIG. 16 (a)), and a potential of the memory cell channel become high (FIG. 16 (b)) at a shared junction between memory cell transistor of CG (n−1) and memory cell transistor of CG (n). In the memory cell of CG (n−1), electrons (●) are accelerated by a high electric field between the source and the drain, and reach to the drain edge (a shared junction among the memory cell transistors), and then a pair of a hot-electron (●) and a hot-hole (∘) generates on a surface at a drain side of the CG (n−1) (★ in FIG. 16 (b)). At this time, if a high potential difference between a gate potential (OV) of CG (n−1) and a potential of a cell channel occurs, the hot-hole flows to a memory cell P-well (GIDL) and the hot-electron is injected into the floating gate of the memory cell transistor in which high electric field is applied, at a certain probability (FIG. 16 (c)). As a result, a threshold of the memory cells of the CG (n) (Vth) becomes higher as programming is performed. Now, if the potential of CG (n) is lowered to a voltage lower than Vpass, it is possible to inhibit the injection of the hot-electrons into the floating gate. However it is difficult to suppress the GIDL to a sufficient level.